1. Field of the Invention
Embodiments of the present invention generally relate to integrated circuits (ICs) and multilayer printed circuit boards (PCBs).
2. Description of the Related Art
As processing applications become increasingly more complex, the number of input/output (I/O) pins, configuration pins, and other types of pins of ICs required for power and to interface with other components continues to grow. It is not uncommon for some application-specific ICs (ASICs) to possess pin counts that exceed 2000. Advancements in technology continually push the envelope to design smaller and smaller surface mount ASICs. Corresponding reductions in package size present a challenge to package designers faced with accommodating the increased pin count.
One approach to meeting the packaging requirements has been to encapsulate ASICs in a surface-mountable ball grid array (BGA). Using a grid of solder balls as its connectors, a BGA enables the package to be only slightly larger than the integrated circuit housed within. All of these trends towards increased functionality in an obligatory diminished package have led to very high density ASICs. However, properly connecting a high density BGA ASIC to a PCB to route signals and maintain signal integrity creates numerous problems for both the ASIC designers and the printed circuit board designers.
Accordingly, techniques for efficiently routing signals from high pin count ICs on multilayer PCBs are needed.
Overview
Embodiments of the present invention provide techniques for optimizing application specific integrated circuit (ASIC) and other integrated circuit (IC) pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout. Such techniques may be applied, for example, in an effort to increase signal integrity and speed, reduce the surface area used by an ASIC and/or its support circuitry, reduce the PCB layer count, reduce plane perforations, and/or reduce via-routed signal crosstalk when compared to conventional layout techniques.
One embodiment of the present invention provides a method. The method generally includes dividing an array of pins of an IC into a plurality of rings, creating a mapping of each of the rings to a net category based on at least one criterion, and assigning each of a plurality of nets of the IC to a pin of one of the plurality of rings based on the mapping.
Another embodiment of the present invention provides a method. The method generally includes classifying nets of an ASIC according to categories based on at least one criterion; dividing an array of pins of the ASIC into rings and quadrants; assigning power nets to pins aggregated at or near a center of the array to form a power core; assigning ground nets to the ASIC pins to form L-shaped patterns; determining a mapping based on the categorized nets and the number of rings; and assigning the remaining nets to the remaining ASIC pins based on the mapping and one of the quadrants corresponding to the general direction in which each of the nets will be routed.
Yet another embodiment of the present invention provides an IC. The IC generally includes a plurality of pins, wherein a first portion of the pins are assigned to ground and arranged in L-shaped patterns.
Yet another embodiment of the present invention provides an IC. The IC generally includes a plurality of pins divided into a plurality of rings. The pins are assigned to signal nets grouped into the plurality of rings according to at least one of signal speed or an amount of associated circuitry.